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a FEATURES All-In-One Synchronous Buck Driver Bootstrapped High Side Drive One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Pulse-by-Pulse Disable Control IN VCC Dual Bootstrapped MOSFET Driver ADP3416 FUNCTIONAL BLOCK DIAGRAM BST DRVH OVERLAP PROTECTION CIRCUIT APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations SW DRVL ADP3416 PGND GENERAL DESCRIPTION The ADP3416 is a dual MOSFET driver optimized for driving two N-channel MOSFETs which are the two switches in a nonisolated synchronous buck power converter. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with "floating" high side gate drivers. The ADP3416 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs. The ADP3416 is specified over the commercial temperature range of 0C to 70C and is available in an 8-lead SOIC package. 7V D1 VCC 12V ADP3416 BST CBST DRVH IN Q1 SW DELAY 1V DRVL 1V PGND Q2 Figure 1. General Application Circuit REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 ADP3416-SPECIFICATIONS1(T = 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V, unless otherwise noted.) A Parameter SUPPLY Supply Voltage Range Quiescent Current PWM INPUT Input Voltage High2 Input Voltage Low2 HIGH SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2) LOW SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2) Symbol VCC ICCQ Conditions Min 4.15 Typ Max 7.5 5 Unit V mA V V ns ns ns ns ns ns ns ns 2 2.3 0.8 VBST - VSW = 5 V VBST - VSW = 7 V VBST - VSW = 5 V VBST - VSW = 7 V VBST - VSW = 7 V, CLOAD = 3 nF VBST - VSW = 7 V, CLOAD = 3 nF VBST - VSW = 7 V VBST - VSW = 7 V VCC = 5 V VCC = 7 V VCC = 5 V VCC = 7 V VCC = 7 V, CLOAD = 3 nF VCC = 7 V, CLOAD = 3 nF VCC = 7 V VCC = 7 V 3.0 2.0 2.0 1.0 25 20 65 25 3.0 2.0 2.0 1.0 25 20 30 15 5.0 4.0 4.0 2.5 40 30 90 35 5.0 4.0 4.0 2.5 40 30 40 25 trDRVH tfDRVH tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 A). 3 AC specifications are guaranteed by characterization but not production tested. 4 For propagation delays, "tpdh" refers to the specified signal going high; "tpdl" refers to it going low. Specifications subject to change without notice. -2- REV. A ADP3416 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Model Temperature Package Range Description 8-Lead Standard Small Outline (SOIC) Package Option SOIC-8 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.0 V to +25 V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0C to 70C Operating Junction Temperature Range . . . . . . 0C to 125C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155C/W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND. ADP3416JR 0C to 70C PIN CONFIGURATION BST 1 IN 2 NC 3 VCC 4 8 DRVH SW PGND DRVL ADP3416 TOP VIEW (Not To Scale) 7 6 5 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin 1 Mnemonic BST Function Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be chosen between 100 nF and 1 F. TTL-level input signal that has primary control of the drive outputs. No Connection. Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck-switching node, close to the upper MOSFET's source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turnon of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high low transition delay is determined at this pin. Buck Drive. Output drive for the upper (buck) MOSFET. 2 3 4 5 6 7 IN NC VCC DRVL PGND SW 8 DRVH CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3416 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -3- ADP3416 IN tpdlDRVL DRVL tfDRVL tpdlDRVH trDRVL tfDRVH tpdhDRVH trDRVH DRVH-SW VTH VTH tpdhDRVL SW 1V Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted) -4- REV. A Typical Performance Characteristics-- ADP3416 50 CLOAD = 3nF T DRVH 5V/DIV R3 TA = 25 C VCC = 5V T TA = 25 C VCC = 5V R3 DRVL 2V/DIV DRVH 5V/DIV TIME - ns 45 DRVH @ VCC = 5V 40 DRVH @ VCC = 7V DRVL @ VCC = 5V 35 IN R2 R1 2V/DIV 40ns/DIV DRVL 5V/DIV R2 R1 30 25 IN 2V/DIV 40ns/DIV DRVL @ VCC = 7V 20 0 25 100 50 75 JUNCTION TEMPERATURE - C 125 TPC 1. DRVH Fall and DRVL Rise Times 35 DRVL @ VCC = 7V 30 25 DRVL @ VCC = 5V TPC 2. DRVL Fall and DRVH Rise Times 55 50 DRVH @ VCC = 5V 45 40 TPC 3. DRVH and DRVL Rise Times vs. Temperature 37 32 DRVL @ VCC = 7V 27 TIME - ns 20 15 10 5 0 DRVH @ VCC = 7V DRVH @ VCC = 5V TIME - ns 35 30 25 20 15 DRVL @ VCC = 5V DRVL @ VCC = 7V TIME - ns DRVH @ VCC = 7V 22 17 DRVH @ VCC = 5V DRVH @ VCC = 7V DRVL @ VCC = 5V 12 0 25 50 75 100 JUNCTION TEMPERATURE - C 125 10 1.0 2.0 3.0 4.0 LOAD CAPACITANCE - nF 5.0 7 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOAD CAPACITANCE - nF 5.0 TPC 4. DRVH and DRVL Fall Times vs. Temperature 35 30 SUPPLY CURRENT - mA 25 VCC = 7V 20 15 10 5 0 VCC = 5V TA = 25 C CLOAD = 3nF TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance 8.5 8.0 SUPPLY CURRENT - mA TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance VCC = 7V 7.5 7.0 6.5 6.0 VCC = 5V 5.5 5.0 CLOAD = 3nF fIN = 250kHz 0 200 400 600 800 1000 1200 1400 IN FREQUENCY - kHz 0 100 25 50 75 JUNCTION TEMPERATURE - C 125 TPC 7. Supply Current vs. Frequency TPC 8. Supply Current vs. Temperature REV. A -5- ADP3416 THEORY OF OPERATION The ADP3416 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high side and the low side FETs. Each driver is capable of driving a 3 nF load. A more detailed description of the ADP3416 and its features follows. Refer to the Functional Block Diagram. Low Side Driver SW Pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. To prevent the overlap of the gate drives during Q2's turn OFF and Q1's turn ON, the overlap circuit provides a internal delay that is set to 50 ns. When the PWM input signal goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay. Once the delay period has expired, Q1 will begin turn ON. APPLICATION INFORMATION Supply Capacitor Selection The low side driver is designed to drive low RDS(ON) N-channel MOSFETs. The maximum output resistance for the driver is 4 for sourcing and 2.5 for sinking gate current. The low output resistance allows the driver to have 40 ns rise and 30 ns fall times into a 3 nF load. The bias to the low side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver's output is 180 degrees out of phase with the PWM input. When the ADP3416 is disabled, the low side gate is held low. High Side Driver The high side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The maximum output resistance for the driver is 4 for sourcing and 2.5 for sinking gate current. The low output resistance allows the driver to have 40 ns rise and 30 ns fall times into a 3 nF load. The bias voltage for the high side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW Pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3416 is starting up, the SW Pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high side driver will begin to turn the high side MOSFET, Q1, ON by pulling charge out of CBST. As Q1 turns ON, the SW Pin will rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW Pin. When the low side MOSFET, Q2, turns ON, the SW Pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high side driver's output is in phase with the PWM input. When the driver is disabled, the high side gate is held low. Overlap Protection Circuit For the supply input (VCC) of the ADP3416, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 1 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: Murata TaiyoYuden Tokin GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP www.murata.com www.t-yuden.com www.tokin.com Keep the ceramic capacitor as close as possible to the ADP3416. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode, as shown in Figure 1. Selection of these components can be done after the high side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 volts. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: CBST = QGATE VBST The overlap protection circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1's turn OFF to Q2's turn ON, and by internally setting the delay from Q2's turn OFF to Q1's turn ON. To prevent the overlap of the gate drives during Q1's turn OFF and Q2's turn ON, the overlap circuit monitors the voltage at the SW Pin. When the PWM input signal goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the overlap protection circuit waits for the voltage at the SW Pin to fall from VIN to 1 V. Once the voltage on the SW Pin has fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage on the where, QGATE is the total gate charge of the high side MOSFET, and VBST is the voltage droop allowed on the high side MOSFET drive. For example, the IRF7811 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high side MOSFET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by: IF(AVG) QGATE x f MAX where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 5 V supply, and the ESR of CBST. -6- REV. A ADP3416 Printed Circuit Board Layout Considerations Typical Application Circuits Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. 2. Connect the PGND Pin of the ADP3416 as close as possible to the source of the lower MOSFET. 3. The VCC bypass capacitor should be located as close as possible to VCC and PGND Pins. The circuit in Figure 3 shows how two drivers can be combined with the ADP3165 to form a total power conversion solution for VCC(CORE) generation in a high current Intel CPU computer. L1 1H VIN12V 270 F/16V 3 OS-CON SP SERIES 18m ESR(EACH) + + C2 + C3 R7 5m 10 F 2 MLCC D1 MBR052LTI Q2 FZ649TA C4 4.7 F R5 20 C6 15nF Z1 ZMM5263BCT VINRTN C1 R4 10 R6 2k U2 100nF ADP3416 1 BST 2 IN 3 NC 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5 Q7 FDB8030L C11 Q3 FDB7030L 2200 F/6.3V 9 L2 RUBYCON MBZ SERIES 600nH 12m ESR(EACH) + + VCC(CORE) 1.1V - 1.85V C13 15nF R8 2 U1 ADP3165 1 VID4 2 VID3 FROM CPU RA 32.4k Q1 2N7000 OUTEN R2 RB 10.0k 3 VID2 4 VID1 5 VID0 6 SHARE 7 COMP 8 GND 9 FB 10 CT C9 150pF R3 1k C18 4.7 F VCC 20 REF 19 PWM1 18 PWM2 17 PWM3 16 PC 15 PGND 14 CS- 13 CS+ 12 PWRGD 11 D3 MBR052LTI C15 4.7 F C7 1nF C12 4.7 F C20 C29 65A VCC(CORE)RTN D2 MBR052LTI U3 100nF ADP3416 1 BST 2 IN 3 NC 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5 Q8 FDB8030L C14 Q4 FDB7030L L3 600nH C16 15nF R9 2 10 F 27 MLCC U5 10k 1/6 7404 COC 1.2nF U4 100nF ADP3416 1 BST 2 IN 3 NC 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5 C17 Q5 FDB7030L L4 600nH C19 15nF R10 2 C10 100pF NC = NO CONNECT Q9 FDB8030L Figure 3. 65 A Intel Pentium 4 CPU, VR Down Guideline Design REV. A -7- ADP3416 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) C02600-0-8/02(A) 45 Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) PIN 1 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA Revision History Location 08/02--Data Sheet changed from REV. 0 to REV. A. Page Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -8- REV. A PRINTED IN U.S.A. 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